Overview
The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data blocks with 128-bit key (a 256-bit key version is available).
Basic core is designed only for encryption and is the smallest available on the market (less than 3,000 gates). Enhanced versions are available that support encryption and decryption for various NIST cipher modes (ECB,CBC, OFB, CFB, CTR), as well as different datapath widths for size/performance tradeoff. The core includes the key expansion logic.
The design is fully synchronous and available in both source and netlist form.
Optional data integrity and differential power attack resistance features.
Learn more about Symmetric Crypto IP core
IP Cores, Inc. announces the release of the new LZR4D single-engine ultralow-latency lossless decompression core for the LZ4 format, delivering 256 bits of decompressed data per clock with less than 30 clock cycles of latency.
IP Cores, Inc. announces shipments of the FFT4T core for RF signal processing systems
IP Cores, Inc. announces shipments of the newly released PQC1 Post-Quantum Cryptography Accelerator Core that supports both ML-KEM (FIPS-203) and ML-DSA (FIPS-204).
IP Cores, Inc., California, USA had announced modifications to its true random number generator IP core, TRNG1.
IP Cores, Inc. has announced that the first shipment of the server memory encryption IP cores occurred one year ago.
IP Cores, Inc., (California, USA, http://www.ipcores.com) has announced modifications of its MSP10-512 cores that support line-speed MACsec encryption and decryption for the 400 Gbps Ethernet.
