Vendor: SmartDV Category: Test / Debug

Twin Quad NOR Flash Memory Model

Twin Quad NOR Flash Memory Model provides an smart way to verify the Twin Quad NOR Flash component of a SOC or a ASIC.

Overview

Twin Quad NOR Flash Memory Model provides an smart way to verify the Twin Quad NOR Flash component of a SOC or a ASIC. The SmartDV's Twin Quad NOR Flash memory model is fully compliant with standard Twin Quad NOR Flash Specification and provides the following features. Better than Denali Memory Models.

Twin Quad NOR Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Twin Quad NOR Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports Twin Quad NOR Flash memory devices like MT25T_QLKT_L_01G_xBB from all leading vendors
  • Supports 100% of Twin Quad NOR Flash protocol standards.
  • Supports all the Twin Quad NOR Flash commands as per the specs.
  • Supports Stacked device (two 512Mb die)
  • Supports Dual/quad I/O instructions
  • Supported protocols in both STR and DTR
    • Extended I/O protocol
    • Dual I/O protocol
    • Quad I/O protocol
  • Supports Execute-in-place (XIP).
  • Supports volatile and nonvolatile configuration settings.
  • Supports software reset.
  • Supports 3-byte and 4-byte addressing modes
  • Supports 64-byte OTP area outside main memory.
    • Readable and user-lockable
    • Permanent lock with Program OTP commands
  • Supports Program/Erase Suspend operation.
  • Supports the following Erase capability
    • Die erase
    • Sector erase 64KB uniform granularity
    • Subsector erase 4KB, 32KB granularity
  • Supports security and write protection
    • Volatile and nonvolatile locking and software write protection
    • Nonvolatile configuration locking
    • Password protection
    • Hardware write protection
    • CRC
  • Supports all types of timing and protocol violation detection.
  • Constantly monitors Twin Quad NOR Flash behavior during simulation.
  • Protocol checker fully compliant with Twin Quad NOR Flash Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

Twin Quad NOR Flash Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of Twin Quad NOR Flash designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the Twin Quad NOR Flash testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
Twin Quad NOR Flash Memory Model
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

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Frequently asked questions about SerDes Test / Debug IP cores

What is Twin Quad NOR Flash Memory Model?

Twin Quad NOR Flash Memory Model is a Test / Debug IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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