Overview
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is included for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings. Remarkable physical flexibility allows the PHY to adapt to each customer’s die floorplan and package constraints, yet is delivered and verified as a single unit for easy timing closure with no assembly required. The PHY is DFI 5.1 compliant, and when combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized.
Learn more about DDR IP core
In wide chip interfaces like DDR, HBM and ONFI, it can be challenging to synthesize and connect high-frequency controllers to the PHY hard macros. Clock trees can be expansive, pushing tools to their limits, and often multiple clock domains are needed.
Selecting PLLs for ASIC Applications Requires Tradeoffs
Brett Murdock, Dana Neustadter (Synopsys)
In recent years, emerging industries such as AI, Internet of Things, 5G, and intelligent networked vehicles have flourished, and the high requirements for performance have greatly increased the scale and complexity of chips, constantly challenging IP limitations.
Dana Neustadter, Senior Product Manager for Security Solutions, and Brett Murdock, Director, Product Line Management for Memory Interface IP, Synopsys Solutions Group
DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
