High-Speed Test IO: Addressing High-Performance Data Transmission And Testing Needs For HPC & AI
Maximize limited package pins with IO that can act as high-speed test ports then be reused as low-power GPIOs during field operation.
Vendor:
Synopsys, Inc.
Category:
GPIO
TSMC 5nm (N5) 1.2V/1.8V I3C Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device.
Overview
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can be controlled by one I3C primary device at a time. It offers backward compatibility with I2C legacy devices, is designed for high I/O voltage domains and supports low-core voltage domains. The I3C incorporates the Schmitt-Trigger function, supports I2C Legacy Fast Mode and FM+ Mode, and includes HBM and CDM ESD protection. We provide an interoperable validated I3C I/O solution with our in-house Synopsys I3C controllers. The library supports independent power sequencing with the support of a power management cell from our base libraries. The Synopsys I3C I/O specifications align with the latest JEDEC standards and support:
Push-pull (12.5 MHz) and Open drain I3C modes (1MHz)
I2C Legacy Fast Mode (400KHz) and Fm+(1MHz) Mode
Push-pull (12.5 MHz) and Open drain I3C modes (1MHz)
I2C Legacy Fast Mode (400KHz) and Fm+(1MHz) Mode
Key features
- Support Schmitt trigger
- 50 ns filter for spike rejection
- Automotive G1/G2 supported, ASIL-B certified
- Silicon-validated IP
- Interoperable validated I3C I/O solution with our in-house Synopsys I3C Controllers
- HBM 2KV, CDM 500V(up to 7A), Latch-up +/-100 mA @ 125C
- Designed to support multiple metal stack options
- Support for flip-chip & wirebond packaging
- Silicon-proven solution
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 5nm | N5 | — |
Specifications
Identity
Part Number
dwc_io_ts5ff_1p8v_i3c
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about GPIO IP core
Improving Inter Integrated Circuits - From Sensor Hubs to Platform Management Solutions
This paper attempts to redefine these existing system level solutions using I3C and examine the improvements it can bring over I2C based solutions. Furthermore, it presents a seamless and risk free migratory path to the industry from these I2C based architectures to I3C based architectures using proven Synopsys Solutions.
Configurable Microprocessor for Life Essential Devices
This paper will explore how processors have evolved with attributes such as configurability and extensibility to enable the next generation of electronics.
Enabling Rapid Adoption of the AMBA 3 AXI Protocol-based Design with Synopsys DesignWare IP
The DesignWare® IP solution for the AMBA 3 AXI protocol enables designers to quickly and easily integrate the high-speed protocol into their (SoC) designs, while reducing risk and speeding time to results
Achieving Your Low Power Goals with Synopsys Ultra Low Leakage IO
This whitepaper explains the need for ULL GPIOs, the optimization techniques used to reduce leakage, and the inherent tradeoffs to consider. Finally, it describes how Synopsys ULL GPIOs help designers reduce leakage while achieving the SoC power and performance targets for mobile and battery-driven devices used in AI and sensing applications.
Android hardware-software design using virtual prototypes - Part 2: Building a sensor subsystem
In the second of a three-part series of articles on virtual prototyping, Achim Nohl explains how to use the Synopsys Virtualizer Development Kit (VDK) and describes the hardware/software integration flow for a sensor subsystem for use in an Android mobile device. For the remainder of this series, we will illustrate virtual prototyping usage and early software development by means of a brief case study. The case study is centered on a multi-function sensor controller subsystem which supports an accelerometer, magnetic field, orientation, gyroscope, light, pressure, temperature, and proximity.
Frequently asked questions about GPIO Pad Library IP cores
What is TSMC 5nm (N5) 1.2V/1.8V I3C Libraries?
TSMC 5nm (N5) 1.2V/1.8V I3C Libraries is a GPIO IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.