Overview
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and high-performance computing (HPC) applications. The IP is silicon-proven and available in several foundries and process technologies from 3nm to 22nm.
Synopsys GPIO library is designed to support multiple voltages; it offers a complete set of support cells (supply, corner spacers, diode breakers, terminators) required to create complete I/O pad rings for system-on-chips (SoCs). The library is compatible with flip-chip packaging. The GPIO driver pad incorporates the Schmitt-Trigger function, programmable drive strength, and pull-up/down resistors, with robust HBM and CDM ESD protection. Synopsys’ broad GPIO IP offering helps achieve your SoC design’s critical power, performance, and area (PPA) requirements, delivering low-risk solutions in a fast time-to-market.
Learn more about GPIO IP core
Recognition highlights leadership in agentic AI design, advanced-node enablement, co-packaged optics, and silicon-proven IP for next-generation AI systems
Leading portfolio of engineering solutions positions Synopsys to capitalize on the continued expansion of digital and physical AI and the AI-driven transformation of engineering.
The companies signed an expansive, multi-year agreement to jointly develop GPT-Synopsys, a specialized model, optimized to use Synopsys EDA tools to perform semiconductor design workflows.
The multi-year agreement marks the expansion of Synopsys' silicon IP business to serve increasing demand for application-optimized IP with Amazon as its lead customer.
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New collaborations span A14 design enablement, AI-assisted engineering workflows, CoWoS® support for multi-die designs, and unified multiphysics signoff
