UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
Vendor:
SmartDV Technologies
Category:
Protocol Bridge
TileLink Assertion IP
TileLink Assertion IP provides an smart way to verify the TileLink component of a SOC or an ASIC.
Overview
TileLink Assertion IP provides an smart way to verify the TileLink component of a SOC or an ASIC. The SmartDV's TileLink Assertion IP is fully compliant with standard TileLink Specification 1.8.1 and provides the following features.
TileLink Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
TileLink Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Specification Compliance
- Compliant with TileLink specification version 1.8.1.
- Supports TileLink Uncached Lightweight (TL-UL), TileLink uncached Heavy weight (TL-UH) and TileLink Cached (TL-C) conformance levels.
- Supports Cache-coherent shared memory.
- Out-of-order completion support.
- Burst fragmentation support.
- Ability to configure the width of all signals.
- On-the-fly protocol and data checking.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV TileLink VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure TileLink Assertion IP functionality.
Block Diagram
TileLink AIP block diagram
Benefits
- Runs in every major formal and simulation environment.
What’s Included?
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
TileLink AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about Protocol Bridge IP cores
What is TileLink Assertion IP?
TileLink Assertion IP is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.