Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: ADC

SMIC 65nm 24Bit Sigma-Delta

The S65LLV25_DAC_01 specifies the design of a high-performance 24-bit stereo Audio DAC for portable digital audio systems.

24 Bit SMIC 65nm LL View all specifications

Overview

The S65LLV25_DAC_01 specifies the design of a high-performance 24-bit stereo Audio DAC for portable digital audio systems. The DAC within the specification uses sigma-delta technique. The output analog signals of S65LLV25_DAC_01 including stereo output are single-ended. The internal stereo headphone amplifier is capable of driving 16Ω load.

Key features

  • Single-ended DAC
  • --LineOut THDN: -91dB@-6dBFS
  • --LineOut Dynamic Range, SNR: 102dB
  • Audio Serial Interface:
  • --32bit word length
  • --I2S mode
  • 2-wire Serial Control Interface
  • Master Clock is 256fs
  • Sampling Rates:
  • --8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz
  • Power Supply:
  • --1.2V Core Digital Supply typ. (1.08~1.32V)
  • --2.5V Pad and Analog Supply typ. (2.25-2.75V)
  • Highly Efficient Linear Headphone Amplifier
  • Internal PLL as the Audio DAC’s master clock generator
  • Output Mux to bypass FM/Sidetone signal to output
  • Out-PGA: 0dB~-60dB, -2dB per step with analog Mute

Silicon Options

Foundry Node Process Maturity
SMIC 65nm LL —

Specifications

Identity

Part Number
S65LLV25_DAC_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Analog

Resolution bits
24 Bit

Provider

Learn more about ADC IP core

VeriSilicon and Google Jointly Launch Open-Source Coral NPU IP

The Coral NPU is built on the open RISC-V instruction set architecture, featuring native tensor processing capabilities, supporting mainstream machine learning frameworks such as JAX, PyTorch, and TensorFlow Lite (TFLite), and utilizing open-standard tools like Multi-Level Intermediate Representation (MLIR) from the Low Level Virtual Machine (LLVM) project for compiler infrastructure.

Frequently asked questions about ADC IP cores

What is SMIC 65nm 24Bit Sigma-Delta?

SMIC 65nm 24Bit Sigma-Delta is a ADC IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic.

How should engineers evaluate this ADC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP