Overview
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes internal sample/hold circuits, a capacitive DAC, a comparator, and logic control circuits. External reference voltage is needed. The voltage reference input can be adjusted to allow encoding from smaller analog voltage span to the full 12 bits of resolution. This ADC has two input modes, i.e., differential and single ended, working in differential mode allows the IP to be insensitive to noise. As to single ended mode, the structure is a little simple. This ADC has two speed modes, i.e., high speed and low speed, working in low speed mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, the SAR will switch to power down mode automatically so as to save power. This ADC has two resolution modes, i.e. 12 bit mode and 8 bit mode In 8 bit mode it could support as high as 4MSPS, while in 12 bit mode it could support 1MSPS. The converter has flexible control logic, and could be easily integrated into a host system. The IP is suitable for integrated auxiliary CODEC applications and multi-converter architectures in wireless or battery-operated products.
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This paper introduces a novel closed-loop testing methodology for efficient linearity testing of high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). Existing test strategies, including histogram-based approaches, sine wave testing, and model-driven reconstruction, often rely on dense data acquisition followed by offline post-processing, which increases overall test time and complexity.
Analog to digital converters have three key input ports along with data output ports as per digital resolution requirements. These inputs ports are Analog Signal, Reference and Clock. If we compare across most of the converter architectures then clock frequency is directly related to output data rate and latency of the data conversion.
The growing availability of digital ICs like microcontrollers, microprocessors, and field-programmable gate arrays (FPGAs) allows developers to use complex digital processing techniques rather than analog signal conditioning. For this reason, analog-to-digital converters (ADCs) have become a widely-used component in mixed-signal circuits.
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
Power-sensitive applications such as Internet-of-Things (IoT) require a comprehensive power savings strategy within the system-on-chip (SoC). Techniques relying solely on the use of traditional power down modes and low supply voltage may not be enough to achieve the required power targets. The analog block is often assumed to be too sensitive and not compatible with aggressive power management techniques.
When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output. To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.
