Overview
This analog-to-digital converter (ADC) uses successive approximation register (SAR) architecture to achieve 12-bit resolution. The ADC includes internal sample/hold circuits, a capacitive DAC, a comparator, and logic control circuits. External reference voltage is needed. The voltage reference input can be adjusted to allow encoding from smaller analog voltage span to the full 12 bits of resolution. This ADC has two input modes, i.e., differential and single ended, working in differential mode allows the IP to be insensitive to noise. As to single ended mode, the structure is a little simple. This ADC has two speed modes, i.e., high speed and low speed, working in low speed mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, the SAR will switch to power down mode automatically so as to save power. This ADC has two resolution modes, i.e. 12 bit mode and 8 bit mode In 8 bit mode it could support as high as 4MSPS, while in 12 bit mode it could support 1MSPS. The converter has flexible control logic, and could be easily integrated into a host system. The IP is suitable for integrated auxiliary CODEC applications and multi-converter architectures in wireless or battery-operated products.
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