Overview
The present IP is a VCC Detector (VDT) circuit which detects the voltage level of its power supplies, AV18 and AV33. The normal operational voltage levels of AV18 and AV33 are 1.62v~1.98v and 3.0v~3.6v respectively. When the detected voltage AV18/AV33 increases across the detection level VR18/VR33, the corresponding output OUTP15/OUTP25 is generated as a high level logic. When the detected voltage AV18/AV33 decreases below the detection level VF18/VF33, the corresponding output OUTP15/OUTP25 is generated as a low level logic. This system consists of two comparator sub-circuits and needs an external bandgap. Moreover, 1.8V power must be ready when 3.3V power is detected, otherwise no correct output is generated. The output may be at wrong voltage level during power-up course before the bandgap becomes stable.
Learn more about Voltage Monitor IP core
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Validation of power supply voltage at the FPGA; real-time monitoring of Vccint power consumption; realistic power estimates using accurate on-die temperature measurement.
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