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This article presents the challenge of pairing an RF analog circuit with the appropriate inductor-based embedded Switching Regulator (namely eSR, equivalent to on-board DC/DC) allowing to meet both the power efficiency requirements and the module performance level at the same time.
Using pulsed latches instead of flip-flops is a solution that has been thoroughly studied for its advantages in speed, density, and power consumption reduction [1] [2]. Even so, this solution has not been widely adopted by standard cell library providers because of the difficulties related to timing verifications: pulse width integrity and hold time closure. There is also a lack of EDA tools natively supporting this feature. Dolphin Integration delivers standard cell libraries based on pulsed latches (SESAME uHD libraries) that can be used in standard design flows and fully compatible with the most common EDA tools.
Developing and verifying a control network in a low-power SoC is a challenging task, especially managing the different states of regulators and modes of power domains.
This article first describes state-of-the-art approaches to addressing this issue, and then delves into the solution promoted by Dolphin Integration to go further, thanks to the easy and secure Maestro� solution to manage SoC power mode transitions.
This article suggests an innovative approach to build an optimal PMNet per application requirements, based on the definition of four standardized voltage levels (further defined as Interfaces for the Distribution of Power). Finally, it demonstrates the advantages of this approach from which regulator suppliers or designers, SoC integrators and system makers can benefit.
Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use.
This paper proposes AIA, an Approximate Inference Accelerator designed to empower decision-making and reasoning at the edge.
