Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
SRAM
Silterra 0.11um ULL Single-Port/Dual-Port SRAM, Single-Port Register File and Via ROM Compiler
VeriSilicon SMSB 0.11um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor …
Overview
VeriSilicon SMSB 0.11um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor Manufacturing Corporation (SMSB) 0.11um 1P8M Ultra Low Leakage 1.5V/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.
VeriSilicon SMSB 0.18 ULL Process Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.
VeriSilicon SMSB 0.18 ULL Process Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
Key features
- Low Leakage
- Low Power
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
- Write Mask Function (SRAM & Register File)
- More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp
Specifications
Identity
Part Number
SMSB11ULL
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Provider
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Frequently asked questions about SRAM IP cores
What is Silterra 0.11um ULL Single-Port/Dual-Port SRAM, Single-Port Register File and Via ROM Compiler?
Silterra 0.11um ULL Single-Port/Dual-Port SRAM, Single-Port Register File and Via ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.