SGRAM Memory Model

SGRAM Memory Model provides an smart way to verify the SGRAM component of a SOC or a ASIC. The SmartDV's SGRAM memory model is fully compliant with standard SGRAM Specification and provides the following features. Better than Denali Memory Models.

SGRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SGRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports SGRAM memory devices from all leading vendors.
• Supports 100% of SGRAM protocol standard IS42G32256-8pQ.
• Supports all the SGRAM commands as per the specs.
• Quickly validates the implementation of the SGRAM standard IS42G32256-8pQ.pdf.
• Supports dual internal banks.
• Supports Mode register and special mode register programming.
• Supports Programmable burst lengths: 1,2,4,8 or full page.
• Supports for Block write and masked write.
• Supports for programmable CAS latency.
• Supports for auto precharge and auto refresh.
• Supports for Power Down features.
• Supports for input clock stop.
• Supports for clock suspend.
• Supports for x32 device type.
• Supports 16MB Memory density.
• Supports for Define Special Function.
• Supports for the following modes of burst type control.
• Basic mode
• Special mode
• Random mode
• Interrupt mode
• Supports for burst terminate.
• Supports the following burst order.
• Sequential
• Interleave
• Supports for self refresh mode.
• Supports data mask for write and block write.
• Checks for following
• Check-points include power up initialization and power off rules,
• State based rules, Active Command rules,
• Read/Write Command rules etc.
• All timing violations.
• Supports for full-timing as well as behavioral versions in one model.
• Supports for all timing delay ranges in one model: min, typical and max.
• Protocol checker fully compliant with SGRAM Specification IS42G32256-8pQ.pdf.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
• Constantly monitors SGRAM behavior during simulation.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor.

• Faster testbench development and more complete verification of SGRAM designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the SGRAM testcases.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.