PowerPC to PCI Bridge
- Protocol Bridge
- Now
- PCI Specification 2.2 Proto…
PowerPC to PCI Bridge
PowerPC Bus Slave
PowerPC Bus Master
PowerPC Bus Arbiter
The system controller core connects the system CPU to system memory, PCI bus, IO ports and external communication links.
CompactFlash/PCMCIA Host Controller with EXCA Registers
CompactFlash/PCMCIA Host Controller with EXCA Registers
DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz.
Advanced 2D Graphics Controller
BADGE works as a graphics engine in embedded systems, but doesn’t suffer from the short life cycles affecting the usual graphics …
Lancero Scatter-Gather DMA Engine for PCI Express
The Lancero Scatter-Gather DMA Engine for PCI Express provides a Target Bridge and/or a Descriptor Bridge SGDMA solution for PCI …
This implementation of the AES-CCM algorithm implements the full NIST draft SP800-38C specification.
The XPS HWICAP (Hardware ICAP) IP enables an embedded microprocessor, such as the MicroBlaze™ or PowerPC™ to read and write the F…
DDR3 SDRAM Controller
SD/SDIO 2.0 MMC Host Controller
The EP550 is a host controller for SD memory card, SDIO and MMC interface.
DDR2 SDRAM Controller
AMBA AHB Bus to SDRAM Controller
AMBA AHB Bus to SDRAM Controller
I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
The DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via th…
Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Int…
I2C Controller IP – Slave, Parameterized FIFO, AHB Bus
The DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 2…
I2C Controller IP – Slave, Parameterized FIFO, APB Bus
The DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP – Slave, Parameterized FIFO, AXI Bus
The DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 4…