SDIO Card Device IP

The SDIO Card Device IP core is used to implement SDIO cards that are connected to a Host processor over a standard SD bus. The flexible architecture of the SDIO Device IP core is targeted to develop a range of portable, low-power cards such as the WiFi (802.11), GPS, WiMAX, UWB, LTE.

The SDIO Card Device IP core is fully compliant with the SD Specification Part E1 SDIO 3.0. It supports SPI, SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full-speed SD data transfers are also supported. All version 3.0 features are supported including the UHS-I, SDHS, miniSDIO, embedded SDIO ATA standard function interface code, and operating voltages 2.7-3.6V or 1.7-1.95V. In applications with an AHB interface, the SDIO 3.0 Device is controlled by an ARM processor.

The SDIO Card Device IP controller includes a bidirectional FIFO that is expandable from 4 x 32-bit to any size required. The core supports asynchronous interrupts to the Host processor for improved performance. It supports suspend/resume operation for improved performance.

The controller integrates a scatter-gather DMA engine automating data transfers between the SDIO card and system memory. The SDIO Card Device Controller IP is available with many system bus interfaces including AHB, AXI, OCP, Avalon, BVCI, SPI and custom buses. The wide selection of interfaces enables the core to integrate effectively SOC designs today.

• Compliant with SD Specification Part E1 SDIO Specification 3.0
• Supports Asynchronous Interrupt to Host controller
• Enhanced power management using new Power State Control function
• Supports Read Wait Control, Suspend/ Resume operations for superior card performance
• High-performance UHS-I (104MB/s)
• Multiple I/O functions and one memory supported
• Host clock rate from 0 to 208 MHz
• Supports SPI, 1-bit, and 4-bit SD modes.
• Optional 8-bit mode for embedded SDIO
• Supports all SDIO form factors including standard, mini and micro SDIO card
• Embedded SDIO ATA interface code
• Bus Master with Scatter Gather DMA
• Dual operating voltage range 2.7V – 3.6V and 1.7V – 1.95V
• Maximum 104 MB/s read/write with 4-bit data lines in SD4 mode
• CRC7 (command), CRC16 (data) integrity
• Supports direct R/W (IO52) and extended R/W (IO53)
• Programmable through AMBA 2.0 AHB bus

• Premier direct support from Arasan IP core designers
• Commercial/industrial standard test bench development platforms
• Customer training available
• RoHS compliant

• Fully compliant core with proven silicon
• Premier direct support from Arasan IP core designers
• Easy-to-use industry standard test environment
• Unencrypted source code allows easy implementation
• Customer training available
• Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass