Scalable Ultra-High Throughput H.264 Encoder − Intra Frames (IDR) Encoding

The UHT-H264E-IDR core is a scalable, ultra-high throughput, hardware H.264 encoder, designed to enable 4K and 8K Ultra HD resolutions in power- and cost-effective FPGA or ASIC implementations. This core is an Intra frames (IDR) only encoder and has the smallest silicon footprint of all our UHT H.264 IP cores. This encoder is most suitable for applications requiring high video quality in relatively low compression ratio working range. Encapsulating the longstanding Alma Technologies expertise with H.264, the UHT-H264E-IDR offers perceptually optimized image quality and includes valuable technology, such as its high-quality, low-latency encoding, using deep sub-frame bitrate regulation.

The UHT-H264E-IDR can be configured to support Baseline, Main and High profiles, 4:2:0 and 4:2:2 chroma sampling, and up to 12-bit per component color depth. It can be also used for high frame rate SD to Full HD interlaced or progressive video encoding. The core is very easy-to-use and integrate in a system. It is an autonomous, CPU/GPU-less, complete H/W implementation, accepting video input in standard raster scanned interleaved order and producing ready-to-use H.264 NAL byte-stream output.

The UHT-H264E-IDR is based on a scalable architecture that uses a configurable number of internal, parallel processing, engines. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC design and operation. In addition to the configurable number of internal engines that matches the throughput requirements to the available silicon speed, the encoder can be further fine-tuned before synthesis to save silicon area by removing features that are not needed in a certain implementation.

The UHT-H264E-IDR core implements a simple and flexible, requests based, external memory interface with independent read and write data paths. The external memory I/F is also designed to be tolerant to memory delays and latencies, which may be present in a shared memory system architecture.

Being carefully designed and rigorously verified the UHT-H264E-IDR is a reliable and easy-to-use and integrate IP.

• Standard Compliant and Standalone Operation
  • Intra frames (IDR) only encoder with full compliance to the ITU-T H.264 specification
  • Constrained Baseline, Main, High 10 intra, High 4:2:2 intra, and High 4:4:4 intra (12 bit 4:2:2 or 4:2:0) profiles encoding
  • 4:2:0 and 4:2:2 YCbCr digital video input
  • 8-, 10- and 12-bit per component color depth encoding
  • ITU-T H.264 Annex B compliant NAL byte-stream output
  • Profile Level up to 5.2
  • No host CPU assisted, autonomous operation
• Advanced H.264 Implementation
  • Perceptually optimized Image Quality
  • Ultra-High throughput using scalable and transparent parallel processing
  • Advanced Intra prediction
    • All 4 Intra 16x16 prediction modes
    • All 4 Intra Chroma prediction modes
    • All 9 Intra 4x4 prediction modes
  • CABAC or CAVLC entropy coding
  • CQP - VBR encoding mode
  • CBR encoding mode
  • One frame algorithmic encoding latency
    • Deep sub-frame bitrate regulation for zero additional latency contribution to the end-to-end latency
  • On-the-fly bitrate changes supported
  • Multiple slices per frame encoding
• Smooth System Integration
  • Full abstraction of the internal implementation details and the H.264 complexity from the top level I/O and its operation
  • Simple, microcontroller like, programming interface
  • High-speed, flow controllable, streaming I/O data interfaces
    • Simple and FIFO like
    • Avalon-ST compliant (ready latency 0)
    • AXI4-Stream compliant
  • Low requirements in external memory bandwidth
  • Flexible external memory interface
    • Independent of external memory type
    • Tolerant to latencies
    • Allows for shared memory access
    • Can optionally operate on independent clock domain
• Trouble-Free Technology Map and Implementation
  • Fully portable, self-contained RTL source code
  • Strictly positive edge triggered design
  • D-type only Flip-Flops
  • Safe CDC transfers when using more than one clock domain
  • No special timing constraints required
    • No false or multi-cycle paths within the same clock domain
    • No CDC transfers that need to be constrained (all CDC paths can be excluded)

• Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices
• Release Notes, Design Specification and Integration Manual documents
• Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts
• Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license
• Self-checking testbench environment sources, including sample BAM generated test cases
• Simulation and sample Synthesis (for ASICs) or Place & Route (for FPGAs) scripts