Vendor: SmartDV Category: DDR

RLDRAM3 Memory Model

RLDRAM3 Memory Model provides an smart way to verify the RLDRAM3 component of a SOC or a ASIC.

Controller View all specifications

Overview

RLDRAM3 Memory Model provides an smart way to verify the RLDRAM3 component of a SOC or a ASIC. The SmartDV's RLDRAM3 memory model is fully compliant with standard RLDRAM3 Specification and provides the following features. Better than Denali Memory Models.

RLDRAM3 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

RLDRAM3 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports RLDRAM3 memory devices from all leading vendors.
  • Supports 100% of RLDRAM3 protocol standard.
  • Supports all the RLDRAM3 commands as per the specs.
  • Supports the following devices.
    • X18
    • X36
  • Supports for SDR addressing.
  • Supports Reduce cycle time (tRC(MIN) = 6.67 - 8ns).
  • Supports Programmable READ/WRITE latency (RL/WL) and burst length.
  • Supports Data mask for WRITE commands.
  • Supports Integrated on-die termination (ODT).
  • Supports Single or multibank writes.
  • Supports Extended Operating range (200-1200MHZ).
  • Supports READ training register.
  • Supports Multiplexed and non-multiplexed addressing capabilities.
  • Supports Mirror function.
  • Supports Output driver and ODT calibration.
  • Supports IEEE 1149.1 compliant JTAG boundary scan.
  • Supports full-timing as well as behavioral versions in one model.
  • Supports for all timing delay ranges in one model: min, typical and max.
  • Protocol checker fully compliant with RLDRAM3 Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
  • Constantly monitors RLDRAM3 behavior during simulation.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

RLDRAM3 Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of RLDRAM3 designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the RLDRAM3 testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
RLDRAM3 Memory Model
Vendor
SmartDV
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about DDR IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about DDR Interface IP

What is RLDRAM3 Memory Model?

RLDRAM3 Memory Model is a DDR IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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