How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
RLDRAM Memory Model
RLDRAM Memory Model provides an smart way to verify the RLDRAM component of a SOC or a ASIC.
Overview
RLDRAM Memory Model provides an smart way to verify the RLDRAM component of a SOC or a ASIC. The SmartDV's RLDRAM memory model is fully compliant with standard RLDRAM Specification and provides the following features. Better than Denali Memory Models.
RLDRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
RLDRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports RLDRAM memory devices from all leading vendors.
- Supports 100% of RLDRAM protocol standard.
- Supports all the RLDRAM commands as per the specs.
- Supports the following devices.
- X32
- X16
- Supports cyclic bank addressing for maximum data out bandwidth.
- Supports non-multiplexed addresses.
- Supports non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch).
- Supports 600 Mb/s/p data rate.
- Supports programmable Read Latency (RL) of 5-8.
- Supports data valid signal (DVLD) activated as read data is available.
- Supports data Mask signals (DM0/DM1) to mask first and second part of write data burst.
- Supports IEEE 1149.1 compliant JTAG boundary scan.
- Supports internal auto precharge.
- Supports programmable clock frequency of operation.
- Supports all types of timing and protocol violation detection.
- Constantly monitors RLDRAM behavior during simulation.
- Protocol checker fully compliant with RLDRAM Specification.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
Block Diagram
RLDRAM Memory Model block diagram
Benefits
- Faster testbench development and more complete verification of RLDRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the RLDRAM testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
RLDRAM Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is RLDRAM Memory Model?
RLDRAM Memory Model is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.