How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
RDRAM Memory Model
RDRAM Memory Model provides an smart way to verify the RDRAM component of a SOC or a ASIC.
Overview
RDRAM Memory Model provides an smart way to verify the RDRAM component of a SOC or a ASIC. The SmartDV's RDRAM memory model is fully compliant with standard RDRAM Specification and provides the following features. Better than Denali Memory Models.
RDRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
RDRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports RDRAM memory devices from all leading vendors.
- Supports 100% of RDRAM protocol standard 1-rimm_288_jp and MC-4R64FKE8S-845.
- Supports all the RDRAM commands as per the specs.
- Quickly validates the implementation of the RDRAM standard 1-rimm_288_jp and MC-4R64FKE8S-845.
- Supports programmable clock frequency of operation.
- Supports for all types of timing and protocol violation detection.
- Supports up to 64MB device density.
- Supports 32 banks.
- Supports X16 device mode.
- Supports for All Mode register programming.
- Checks for following
- Check-points include power on, Initialization and power off rules
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Supports for Serial presence detect support.
- Supports for Low Power modes.
- Supports for self-refresh modes.
- Supports for input clock stop and frequency change.
- Protocol checker fully compliant with RDRAM Specification 1-rimm_288_jp and MC-4R64FKE8S-845 compliant.
- Notifies the test bench of significant events such as transactions, warnings, timing :and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
Block Diagram
RDRAM Memory Model block diagram
Benefits
- Faster testbench development and more complete verification of RDRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the RDRAM testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
RDRAM Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is RDRAM Memory Model?
RDRAM Memory Model is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.