PSRAM/RPC PHY & Controller

The DDR IP Mixed-Signal MR PSRAM PHY and RPC PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM/RPC devices. It is optimized for low-power and high-speed applications with robust timing and small silicon area. The PSRAM PHY supports AP memory UHS/OPI PSRAM components on the market, and the RPC PHY supports ETRON components on the market. The PHY components contain PSRAM-/RPC-specialized IO devices for utility and functionality, critical timing synchronization module (TSM), low-jitter PLL, the TX, and RX logic control for the interface.

The’s comprehensive product portfolio also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and stay ahead in the competitive landscape of high-performance memory solutions.

• PSRAM:
  • Supports rates from 200Mbps up to 1600Mbps
  • x8/x16 data bus width extendable
  • 1.8V/2.5V IO devices
  • Multiple drive strengths adjustable
  • Supports read and write timing adjustments with soft calibration
  • Low latency with programmable timings for secure data handling
  • Per bit de-skew support for high speed
  • Supports point-to-point memory sub-systems and multi-rank
  • Supports ZQ calibration to calibrate driver output resistance and on-die termination resistance
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion
  • Various power-down modes for low power including self-refresh support
  • Low jitter with superior noise rejection
  • APB Port register access interface
• RPC:
  • Fully compliant with standards
  • Compliant with DFI specification with the clock rate ratio of 1:2 between controller and PHY
  • Controller CPU bus core could be carried on AXI bus interface
  • Supports 4-port switching with respective FIFO set space for each AXI port
  • Automatic initialization and refresh procedure
  • Pipeline design enables high clock rates with minimal routing constraints
  • Run-time configurable timing parameters
  • Supports RPC device self-refresh and half-refresh mode
  • Source code license available in Verilog HDL
  • Core data path tailored to FPGA family and/or ASIC library

• Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
• Zero risk with robust ESD architecture
• Extensive EDA tool support for various design and automation flow
• Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self-refresh mode
• Comprehensive observation registers DFX and methods are available to facilitate customers in identifying issues during testing

• Extensive documentation
• Models
• LIB
• LEF
• Place-and-route abstracts
• LVS netlist
• GDSII files