PSRAM Memory Model

PSRAM Memory Model provides an smart way to verify the PSRAM component of a SOC or a ASIC. The SmartDV's PSRAM memory model is fully compliant with standard PSRAM Specification and provides the following features. Better than Denali Memory Models.

PSRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

PSRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Supports PSRAM memory devices from all leading vendors
• Supports 100% of PSRAM protocol standard PSRAM Specification
• Supports all the PSRAM commands as per the specs
• Quickly validates the implementation of the PSRAM standard PSRAM Specification
• Supports Asynchronous and page mode interface
• Supports a burst length of 4, 8, or 16 words.
• Supports Mixed mode operation.
• Supports up to 1GB device density.
• Support PROGRAM or ERASE operations.
• Supports Dual voltage rails for optional performance
• Supports Random access time: 55ns and 70ns
• Supports following Page mode read access
• 16-word page size
• Interpage read access: 55ns and 70ns
• Intrapage read access: 15ns and 20ns
• Support following Low power consumption
• Asynchronous READ
• Intrapage READ
• Standby
• Deep power-down (DPD)
• Supports following Low-power features
• Partial-array refresh (PAR)
• DPD mode
• Supports for Synchronous/asynchronous read
• Synchronous burst read mode
• Random access: 70ns
• Asynchronous page mode: 20ns
• Supports for Partial-array self-refresh (PAR)
• Supports for Automatic temperature-compensated self-refresh (TCSR) for power saving
• Separated I/O power(VccQ) & Core power(Vcc)
• Supports Three state outputs
• Supports Byte read/write control by UB#/LB#
• Supports for 8 page mode & DPD
• Supports following Low Power Feature
• Temperature Controlled Refresh
• Partial Array Refresh
• Deep power-down (DPD) mode
• Supports for full-timing as well as behavioral versions in one model.
• Supports for all timing delay ranges in one model: min, typical and max.
• Constantly monitors PSRAM behavior during simulation.
• Protocol checker fully compliant with PSRAM Specification.
• Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
• Built in functional coverage analysis.
• Supports Callbacks, so that user can access the data observed by monitor

• Faster testbench development and more complete verification of PSRAM designs.
• Easy to use command interface simplifies monitor control and configuration.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the PSRAM testcases.
• Complete UVM/OVM sequence library for PSRAM controller.
• Examples showing how to connect and usage of Model.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.