Racyics UCIe PHY IP for GlobalFoundries 22FDX reaches silicon

September 28, 2026 − Chiplet architectures enable complex systems to be built by combining multiple dies within a single package. For this approach, standardized die-to-die communication is essential. Universal Chiplet Interconnect Express (UCIe) provides a common interface for connecting chiplets and enables scalable integration across different applications.

The Racyics® UCIe PHY IP for GlobalFoundries® 22FDX® provides the physical layer for this die-to-die communication. It connects the UCIe Raw Die-to-Die Interface with the electrical mainband and sideband links and extends our 22FDX® IP portfolio with an energy-efficient interconnect solution for consumer and automotive applications.

Designed for UCIe standard package configurations, the PHY supports an x16 data width and data rates of 4 and 8 Gbit/s per pin. The IP integrates both transmitter and receiver functionality together with the required clock generation, link training and resistance calibration. Its Automotive Grade 1 reliability profile also enables the use of the PHY in demanding automotive applications.

With UCIE_PHY_TC1, we have now brought our UCIe PHY implementation to silicon. The dedicated test chip enables silicon validation and characterization of the PHY and represents an important step towards a silicon-proven UCIe solution for GlobalFoundries 22FDX®.

Explore Racyics IP:

• Universal Chiplet Interconnect Express PHY IP - GLOBALFOUNDRIES® 22FDX®

The test chip allows us to evaluate the UCIe PHY under real operating conditions and verify the interaction of its different components on silicon. The resulting measurements provide the basis for further characterization and validation of the IP.

For more technical details and specifications, take a look at our UCIe PHY Product Sheet.