What is 1MHz-50GHz Programmable Prescaler - Divider by 1/2/4/8/16 in SiGe?
1MHz-50GHz Programmable Prescaler - Divider by 1/2/4/8/16 in SiGe is a PLL IP core from Pacific MicroCHIP Corp. listed on Semi IP Hub. It is listed with support for tower.
Vendor:
Pacific MicroCHIP Corp.
Category:
PLL
1MHz-50GHz Programmable Prescaler - Divider by 1/2/4/8/16 in SiGe
The PMCC_DIV50G1_16 is a high speed (up to 50GHz) fully differential programmable divider IP block, designed using Jazz SiGe120 (…
Overview
The PMCC_DIV50G1_16 is a high speed (up to 50GHz) fully differential programmable divider IP block, designed using Jazz SiGe120 (SBC18HX) technology. Divider selectable coefficients are /1 (bypass), /2, /4, /8 and /16. Differential architecture ensures substrate and power supply noise immunity. Macro features optional 50 Ohm terminated input and output (except bypass mode) buffer. Built-in power-down mode enables power saving in case when block is not operated. Operation frequencies, I/O signal levels, control functions and features can be customized upon special agreement.
Key features
- Maximum input frequency: 50GHz
- Supply voltage: 3.3V ±5%
- Power consumption:
- / 1 : 24mW
- / 2 : 45mW
- / 4 : 68mW
- / 8 : 80mW
- /16: 94mW
- Fully differential architecture
- Layout area: 200 x 100 um
Benefits
- Applications:
- Phase–locked loop (PLL) applications from DC to 50 GHz
- Point-to-point and point-to-multipoint radios
- Broadband test and measurement equipment
- Radar, electronic warfare, avionics, and space
What’s Included?
- GDS II file
- Netlist for Spectre simulation
- Layout and Schematic (DRC & LVS) verification reports
- Complete macro datasheet
- Macro integration/application notes
- Design kit and software related information
- Optional deliverables are:
- Library containing entire hierarchy of macro schematic and layout cells
- Extracted views containing parasitic components from layout
- Verilog-A model replicating macro functionally
- Simulation test-benches
- Optional components specific to macro: biasing, specialized I/Os, glue-logic, transmission lines etc.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Tower | 180nm | SL | — |
Specifications
Identity
Part Number
PMCC_DIV50G1_16
Vendor
Pacific MicroCHIP Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Frequently asked questions about PLL IP cores
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.