Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
SmartDV Technologies
Category:
SRAM
Parallel PCM Memory Model
Parallel PCM Memory Model provides an smart way to verify the Parallel PCM component of a SOC or a ASIC.
Overview
Parallel PCM Memory Model provides an smart way to verify the Parallel PCM component of a SOC or a ASIC. The SmartDV's Parallel PCM memory model is fully compliant with standard Parallel PCM Specification and provides the following features. Better than Denali Memory Models.
Parallel PCM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Parallel PCM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports Parallel PCM memory devices from all leading vendors.
- Supports 100% of Parallel PCM protocol standard.
- Supports all the Parallel PCM commands as per the specs.
- Supports device density up to 128MB.
- Supports Serial peripheral interface (SPI).
- Supports high performance Read
- 115ns initial Read access
- 135ns initial Read access
- 25ns, 8-word asynchronous-page Read
- Supports Phase change memory (PCM).
- Supports One-time programmable registers
- Supports 64 unique factory device identifier bits
- Supports 2112 user-programmable OTP bits
- Supports Selectable OTP space in main array
- Supports Power transition Erase/Program lockout.
- Supports Individual zero-latency block locking.
- Supports Individual block lock-down.
- Checks for following
- Check-points include power on, Initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc.
- All timing violations.
- Quickly validates the implementation of the standard Parallel PCM specification.
- Bus-accurate timing for min, max and typical values.
- Constantly monitors Parallel PCM behavior during simulation.
- Protocol checker fully compliant with Parallel PCM Specification.
- Notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
Block Diagram
Parallel PCM Memory Model block diagram
Benefits
- Faster testbench development and more complete verification of Parallel PCM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the Parallel PCM testcases.
- Complete UVM/OVM sequence library for Parallel PCM controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
Parallel PCM Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about SRAM IP cores
What is Parallel PCM Memory Model?
Parallel PCM Memory Model is a SRAM IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.