Vendor: SmartDV Category: Test / Debug

Parallel NOR Flash Synthesizable Transactor

Parallel NOR Flash Synthesizable Transactor provides a smart way to verify the Parallel NOR Flash component of a SOC or a ASIC in…

Overview

Parallel NOR Flash Synthesizable Transactor provides a smart way to verify the Parallel NOR Flash component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's Parallel NOR Flash Synthesizable Transactor is fully compliant with standard Parallel NOR Flash Specification and provides the following features.

Key features

  • Supports 100% of Parallel NOR Flash protocol standard
  • Supports all the Parallel NOR Flash commands as per the specs
  • supports asynchronous random/page read:
    • Page size : 16 words or 32 bytes
    • Page access : 20ns
  • Supports buffer program (512-word program buffer):
    • 2.0 MB/s when using full buffer program
    • 2.5 MB/s when using accelerated buffer program
  • Supports word/byte program
  • Supports block erase (128KB)
  • Supports the following memory densities:
    • 128 MB
    • 256 MB
    • 512 MB
    • 1 GB
    • 2 GB
  • Supports memory organization:
    • Uniform blocks : 128KB or 64KW each
    • x8/x16 data bus
  • Supports program/erase suspend and resume operation:
    • Read from another block during a program suspend operation
    • Read or program another block during an erase suspend operation
  • Supports blank check operation to verify an erased block
  • Supports cyclic redundancy check (CRC) operation
  • Supports unlock bypass, block erase, chip erase and write to buffer capability
  • Supports all types of timing and protocol violation detection
  • Supports extended memory blocks
  • Supports security and write protection:
    • Nonvolatile protection
    • Volatile protection
    • Password protection
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

Parallel NOR Flash Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the Parallel NOR Flash testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
Parallel NOR Flash Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Test / Debug IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about SerDes Test / Debug IP cores

What is Parallel NOR Flash Synthesizable Transactor?

Parallel NOR Flash Synthesizable Transactor is a Test / Debug IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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