Vendor: SmartDV Technologies Category: Test / Debug

Parallel NOR Flash Memory Model

Parallel NOR Flash Memory Model provides an smart way to verify the Parallel NOR Flash component of a SOC or a ASIC.

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Overview

Parallel NOR Flash Memory Model provides an smart way to verify the Parallel NOR Flash component of a SOC or a ASIC. The SmartDV's Parallel NOR Flash memory model is fully compliant with standard Parallel NOR Flash Specification and provides the following features. Better than Denali Memory Models.

Parallel NOR Flash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Parallel NOR Flash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports Parallel NOR Flash memory devices from all leading vendors.
  • Supports 100% of Parallel NOR Flash protocol standard.
  • Supports all the Parallel NOR Flash commands as per the specs.
  • Supports Asynchronous random/page read
    • Page size : 16 words or 32 bytes
    • Page access : 20ns
  • Supports Buffer program (512-word program buffer)
    • 2.0 MB/s when using full buffer program
    • 2.5 MB/s when using accelerated buffer program
  • Supports Word/Byte program.
  • Supports Block erase (128KB).
  • Supports the following memory densities
    • 128 MB
    • 256 MB
    • 512 MB
    • 1 GB
    • 2 GB
  • Supports Memory organization
    • Uniform blocks : 128KB or 64KW each
    • x8/x16 data bus
  • Supports Program/erase suspend and resume operation
    • Read from another block during a PROGRAM SUSPEND operation
    • Read or Program another block during an ERASE SUSPEND operation
  • Supports BLANK CHECK operation to verify an erased block.
  • Supports CYCLIC REDUNDANCY CHECK (CRC) operation.
  • Supports Unlock bypass, block erase, chip erase and write to buffer capability.
  • Supports all types of timing and protocol violation detection.
  • Supports extended memory blocks.
  • Supports security and write protection
    • Nonvolatile protection
    • Volatile protection
    • Password protection
  • Constantly monitors Parallel NOR Flash behavior during simulation.
  • Protocol checker fully compliant with Parallel NOR Flash Specification.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

Parallel NOR Flash Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of Parallel NOR Flash designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the Parallel NOR Flash testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
Parallel NOR Flash Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about SerDes Test / Debug IP cores

What is Parallel NOR Flash Memory Model?

Parallel NOR Flash Memory Model is a Test / Debug IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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