Vendor: SmartDV Technologies Category: Protocol Bridge

OCP Verification IP

OCP Verification IP provides an smart way to verify the OCP component of a SOC or a ASIC.

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Verification IP View all specifications

Overview

OCP Verification IP provides an smart way to verify the OCP component of a SOC or a ASIC. The SmartDV's OCP Verification IP is fully compliant with standard OCP Specification 3.1 and provides the following features.

OCP Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

OCP Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Compliant with OCP 3.1 specification.
  • Supports OCP Master, OCP Slave, OCP Monitor and OCP Checker.
  • Supports all OCP protocol transfer & command types.
  • Supports all OCP protocol signal widths including address and data.
  • Supports all OCP protocol burst models, burst lengths and response types.
  • SRMD and MRMD bursts support.
  • Ability to pipeline transfers and non-blocking flow control support.
  • Supports concurrency and out-of-order processing of transfers: Multi-threading and tagging support.
  • Request interleaving support.
  • Master/Slave Connect-Disconnect feature support.
  • Supports 2-Dimensional block burst address sequences.
  • Compliance to phase-ordering rules.
  • Complete support for full range of OCP configurations.
  • Asynchronous/synchronous reset and EnableClk mechanism. On the fly reset control.
  • Support for ThreadBusy behavior.
  • Supports all sideband signals.
  • Coherence Extensions support.
  • Consistency checks for configuration parameters.
  • Slave supports fine grain control of response per address or per transfer.
  • Supports constrained randomization of protocol attributes.
  • Programmable Timeout insertion.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control OCP functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in master, slave and monitor for various events.
  • Status counters for various events on bus.
  • OCP Verification IP comes with complete testsuite to test every feature of OCP 3.1 specification.

Block Diagram

OCP VIP block diagram

Benefits

  • Faster testbench development and more complete verification of OCP designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the OCP testcases.
  • Examples showing how to connect various components and usage of BFM and Monitor.
  • Detailed documentation of all classes, tasks and functions used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
OCP VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about Protocol Bridge IP cores

What is OCP Verification IP?

OCP Verification IP is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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