Multi-format Video Deinterlacer

The DEINTERLACER IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format.

The deinterlacer allows for three possible filter algorithms - either BOB, ELA or LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field. For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach.

Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges.

Pixels flow into the module in accordance with the valid-ready pipeline protocol. The pixel, sync flags and field number are transferred into the deinterlacer on a rising clock-edge when pixin_val and pixin_rdy are both active high. At the output interface, pixels and syncs are valid on a rising clock-edge when pixout_val is high.

Input lines are buffered and organised spatially before being filtered according to the chosen algorithm. Each input field is converted to a single output frame with twice the number of lines per field.

• Synthesizable, technology independent IP Core for FPGA and ASIC
• Supplied as human readable VHDL (or Verilog) source code
• 24-bit RGB video support with option for YCbCr video formats if required
• Generates clean and progressive video output without combing or tearing
• Reduced softening and sawtooth artefacts
• Supports three different de-interlacing modes including: Interpolated BOB, ELA (Edge-based Line-Average) and a customized version of LCI (Low-Complexity Interpolation)
• Supports all interlaced video formats up to 4096 x 4096 pixels in resolution. Examples include: 480i, 576i, 1080i etc.
• Output is one frame per interlaced field
• Fully pipelined architecture with simple flow-control
• No frame buffer required
• Supports 200MHz+ operation on basic FPGA devices

• High-quality video de-interlacing without the overhead of a frame buffer
• Conversion of 'legacy' SDTV formats to HDTV video formats
• Generating progressive RGB video via inexpensive PAL/NTSC decoder chips
• Digital TV set-top boxes and home media solutions