Vendor: Allegro DVT Category: Video Processing

Multi-format, multi-stream real-time hardware decoder IP core

D300 Series is the ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers lo…

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Overview

D300 Series is the ultimate multi-format, multi-stream real-time hardware decoder IP core, for all semiconductor manufacturers looking to integrate a high-performance video decoding solutions into their chips. Built upon a true multi-format architecture, the D300 Series Decoder IP core provides highly scalable solution up to 8K resolution through their multi-core architecture and selectable video codecs.

The D300 Series Decoder IP core also generalizes the ultra-low latency decoding down to sub-frame latency for all mainstream video formats: H.265, H.264 and JPEG. With 8-, 10- and 12-bit support and supporting chroma sampling of 4:2:0, 4:2:2 and 4:4:4, this decoder core is truly market leading.

Supported formats

  • H.265 Main, Main 10 and 4:2:2, 4:4:4 profiles
  • H.264 Baseline, Main, High, 4:2:2, 4:4:4 profiles
  • 8-bit, 10-bit, 12-bit color depth
  • JPEG Baseline
  • AV1 Main and professional Profile
  • VP9 Profile 0, Profile 1, Profile 2
  • VVC Main 10 and Main 10 4:4:4

Interfaces

  • AMBA APB interface for control registers
  • AMBA AXI interfaces for data access

Key features

  • Supported formats
    • AV1 Main profile (4:2:0 8/10-bit) and Professional profile (4:2:2 10-bit)
    • VP9 Profile 0 (4:2:0 8-bit), Profile 2 (4:2:0 10-bit) and Profile 3 (4:2:2 10-bit)
    • H.265/HEVC Main, Main 10, Main 12, Main 4:2:2 12 and Main 4:4:4 12 profiles, up to Level 6.1 – Main tier and High tier
    • H.264/AVC Constrained Baseline, Main, High, High 10, High 4:2:2 and High 4:4:4 Predictive profiles, up to Level 6.1
    • JPEG Baseline
  • Interfaces
    • AMBA APB interface for control registers programming
    • AMBA AXI interfaces for data access

What’s Included?

  • RTL source code
  • C control software
  • Bit accurate executable software reference model
  • Documentation

Specifications

Identity

Part Number
D300 Series
Vendor
Allegro DVT
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Allegro DVT
HQ: France
Contact Allegro DVT

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is Multi-format, multi-stream real-time hardware decoder IP core?

Multi-format, multi-stream real-time hardware decoder IP core is a Video Processing IP core from Allegro DVT listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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