Vendor: SmartDV Technologies Category: MIPI

MIPI TWP Verification IP

The SmartDV's MIPI TWP Verification IP is fully compliant with Version 1.1 and verifies the TWP Interface.

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Verification IP View all specifications

Overview

The SmartDV's MIPI TWP Verification IP is fully compliant with Version 1.1 and verifies the TWP Interface. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

MIPI TWP Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI TWP Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Compliant with MIPI TWP Specification version 1.1.
  • Supports ATB interface.
  • Supports allows up to 111 source trace streams to be represented as a single stream and later separated by either hardware or software.
  • Supports require low additional bandwidth.
  • Supports minimize the amount of on-chip storage required to generate the protocol.
  • Supports to permits any source trace stream to be used, regardless of its dataformat.
  • Supports for a bit stream that can be exported using any transport that supports bit stream data.
  • Supports to be efficiently stored to memory whose width is a power of two for later retrieval.
  • Supports synchronization points so decode can be accomplished even if the start of the trace is lost.
  • Supports to indicate the Debug and Test Controller (DTC) the position of a trigger event, which is typically used to control actions in the DTC, for example to control trace data capture.
  • Supports to pad the data output for scenarios where a transport interface cannot be idled and valid data is not available.
  • Complete MIPI TWP DTS/DTC functionality.
  • Supports MIPI TWP interface between DTS and DTC.
  • Supports different types of layers
    • Flow Control
    • Alignment Synchronization
    • Data
  • Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Supports constraints Randomization.
  • Callbacks in Master, Slave and Monitor for user processing of data.
  • MIPI TWP Verification IP comes with complete test suite to test every feature of MIPI TWP specification.
  • Functional coverage for complete MIPI TWP features.

Block Diagram

MIPI TWP VIP block diagram

Benefits

  • Faster testbench development and more complete verification of MIPI TWP designs.
  • Easy to use command interface simplifies testbench control and configuration of Master,Slave and Monitor.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the MIPI TWP testcases.
  • Examples showing how to connect various components, and usage of Master,Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
MIPI TWP VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about MIPI IP cores

What is MIPI TWP Verification IP?

MIPI TWP Verification IP is a MIPI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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