MIPI STP Verification IP

The SmartDV's MIPI STP Verification IP is fully compliant with Version 2.0, 2.2 and 2.3 MIPI STP specification and verifies the System Trace Protocol Interface. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.

MIPI STP Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI STP Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Compliant with MIPI STP Specification version 2.0, 2.2 and 2.3.
• Supports STP interface.
• Supports ATB interface.
• Supports TPIU interface.
• Supports a trace stream comprised of 4-bit and 1-bit frames.
• Supports for merging trace data from up to 65536 independent data sources (Masters).
• Supports up to 65536 independent data Channels per Master.
• Supports basic trace data messages that can convey 4, 8, 16, 32, or 64 bit wide data.
• Supports Time-stamped data packets using one of several time stamp formats including:
• Gray code
• Natural binary
• Natural binary delta
• Export buffer depth (legacy STPv1 timestamp that requires DTC support)
• Supports Data packet markers to indicate packet usage by higher-level protocols.
• Supports Flag packets for marking points of interest (for higher-level protocols) in the stream.
• Supports Packets for aligning time stamps from different clock domains.
• Supports Packets for indicating to the DTC the position of a trigger event, which is typically used to control actions in the DTC.
• Supports Packets for cross-synchronization events across multiple STP sources.
• Supports Packets for platform and trace source description.
• Supports for user-defined data packets.
• Facilities for synchronizing the trace stream on bit and message boundaries.
• Supports all types of error insertion and detection.
• Invalid Time-stamp format
• Invalid opcode
• Invalid async pattern
• Invalid version
• Supports constraints randomization.
• Status counters for various events in bus.
• Callbacks in Master and Slave for various events.
• MIPI STP Verification IP comes with complete testsuite to verify each and every feature of MIPI STP specification.
• Functional coverage for complete MIPI STP features.

• Faster testbench development and more complete verification of MIPI STP designs.
• Easy to use command interface simplifies testbench control and configuration of Master,Slave and Monitor.
• Simplifies results analysis.
• Runs in every major simulation environment.

• Complete regression suite containing all the MIPI STP testcases.
• Examples showing how to connect various components, and usage of Master,Slave and Monitor.
• Detailed documentation of all class, task and function's used in verification env.
• Documentation also contains User's Guide and Release notes.