Vendor: SmartDV Category: MIPI

MIPI SPP Synthesizable Transactor

MIPI SPP Synthesizable Transactor provides a smart way to verify the MIPI SPP component of a SOC or a ASIC in Emulator or FPGA pl…

Overview

MIPI SPP Synthesizable Transactor provides a smart way to verify the MIPI SPP component of a SOC or a ASIC in Emulator or FPGA platform. MIPI SPP Synthesizable Transactor provides an smart way to verify the MIPI SPP bi-directional two-wire bus. The SmartDV's MIPI SPP Synthesizable Transactor is fully compliant with Specification for SPP version 1.0 and provides the following features.

Key features

  • Compliant with MIPI SPP version 2.0 specification.
  • Full MIPI Debug functionality.
  • Supports all Debug CCC's and Opcodes
  • Supports Error handling methods
  • Action and Event indications and opcode related to JTAG in the sneakpeek pockets
  • Supports below two different header structurs
    • For high speed mode full sneakpeek
    • For low band width TinnySPP(4Byte header derivative of SPP)
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • Supports on-the-fly protocol and data checking
  • Ability to transmit strings to help verification of SOC
  • Notifies the test bench of significant events such as transactions, warnings,and protocol violations
  • MIPI SPP Synthesizable VIP comes with complete test suite to verify each and every feature of MIPI SPP specification
  • Status counters for various events in bus

Block Diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the MIPI SPP testcases
  • Examples showing how to connect various components, and usage of Synthesiable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
MIPI SPP Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: India

Learn more about MIPI IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about MIPI IP cores

What is MIPI SPP Synthesizable Transactor?

MIPI SPP Synthesizable Transactor is a MIPI IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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