Vendor: SmartDV Technologies Category: MIPI

MIPI SPMI Verification IP

MIPI SPMI Verification IP provides an smart way to verify the MIPI SPMI bi-directional two-wire bus.

Contact Provider Request Datasheet
Verification IP View all specifications

Overview

MIPI SPMI Verification IP provides an smart way to verify the MIPI SPMI bi-directional two-wire bus. The SmartDV's MIPI SPMI Verification IP is fully compliant with version 1.0 and 2.0 MIPI Alliance specification for System Power Management Interface and provides the following features.

MIPI SPMI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI SPMI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports 1.0 and 2.0 MIPI SPMI Specification.
  • Full MIPI SPMI Master and Slave functionality.
  • Operates as a Master, Slave, or both.
  • Monitor, Detects and notifies the testbench of all protocol and timing errors.
  • Supports all topologies as per the MIPI SPMI specification.
  • Supports multiple slaves and multiple masters.
  • Compares read data with expected results.
  • Support for slave requests through Alert bit.
  • Support for slave request hold.
  • Supports following master bus connecting on bus.
    • Connecting by detecting SSC
    • Connecting by detecting Bus idle
    • Connecting by detecting Bus arbitration
  • Supports following frames.
    • Command Frame
    • Data/Address Frame
    • No Response Frame
  • Supports all types of SPMI commands.
  • Support ACK/NACK generation as per 2.0 specs.
  • Supports all power mode commands.
  • Supports Group Slave ID.
  • Various kind of Master and Slave errors generation.
    • Undefined command frame
    • Command frame with parity error
    • Command frame length error
    • Address frame with parity error
    • Data frame with parity error
    • Read of unused register
    • Write of an unused register
    • Read using the broadcast ID or a GSID
    • ACK/NACK errors.
  • Glitch monitor and injection.
    • Support injection of glitch at all positions of SDATA
    • Support injection of glitch at all positions of SCLK
    • Supports detection of glitches
  • Supports extended register read/writes.
  • Supports device enumeration.
  • Supports master and slave arbitration.
  • Bus-accurate timing.
  • Supports half speed and full speed mode.
  • Callbacks in master and slave for various events.
  • Status counters for various events in bus.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Functional coverage of complete MIPI SPMI specs.
  • MIPI SPMI Verification IP comes with complete testsuite to test every feature of MIPI SPMI specification.

Block Diagram

MIPI SPMI VIP block diagram

Benefits

  • Faster testbench development and more complete verification of MIPI SPMI designs.
  • Easy to use command interface simplifies testbench control and configuration of master, slave and monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the MIPI SPMI testcases.
  • Examples showing how to connect various components, and usage of Master, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
MIPI SPMI VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about MIPI IP core

M31 High-Speed and Long-Channel MIPI C/D-PHY Solution on TSMC N3P/N3C

With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.

MIPI CCI over I3C: Faster Camera Control for SoC Architects

Imagine a camera subsystem that responds in microseconds, consumes less power, and offers a more straightforward route to time-to-market. For SoC architects and IP integration teams, that vision is increasingly possible with MIPI Camera Control Interface (CCI) over I3C.

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing performance demands. MIPI MPHY is a high-speed physical layer interface developed by the MIPI Alliance. This protocol is used for high-speed chip-to-chip interfaces, mainly in mobile and automotive devices.

MIPI: Powering the Future of Connected Devices

From the first monochrome mobile displays to today’s ultra-high-definition automotive dashboards and immersive AR/VR headsets, MIPI technology has quietly become the backbone of modern data connectivity. Let’s explore how MIPI standards have evolved, the markets they serve, and why Rambus is at the forefront of this transformation.

Frequently asked questions about MIPI IP cores

What is MIPI SPMI Verification IP?

MIPI SPMI Verification IP is a MIPI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP