Vendor: SmartDV Technologies Category: MIPI

MIPI SPMI Master IIP

MIPI SPMI Master interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI sp…

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Overview

MIPI SPMI Master interface provides full support for the two-wire MIPI SPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI SPMI Master IIP is proven in FPGA environment. The host interface of the MIPI SPMI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI SPMI Master IIP is supported natively in Verilog and VHDL

Key features

  • Supports 2.0 and 1.0 MIPI SPMI Specification
  • Full MIPI SPMI Master functionality
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
  • Supports ACK/NACK as per 2.0 specs
  • Glitch suppression (optional).
  • Supports transfer Bus Ownership Command Sequence.
  • Supports Connect/Disconnect Sequence.
  • In built Host controller interface for command queue based Master command processing (Optional). HCI contains DMA engine
  • Support Master priority arbitration
  • Supports extended register read/writes
  • Supports Baud rate control
  • Supports Low power modes
  • Supports wakeup command
  • Supports Authentication Command Sequence
  • Device Descriptor Block command Sequences
  • Supports baud rate control
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

Block Diagram

MIPI SPMI Master IIP block diagram

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The MIPI SPMI Master interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.
  • ISO26262 Safety Manual (SAM) Document
  • ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document

Specifications

Identity

Part Number
MIPI SPMI Master IIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about MIPI IP cores

What is MIPI SPMI Master IIP?

MIPI SPMI Master IIP is a MIPI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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