Vendor: Synopsys, Inc. Category: MIPI PHY

MIPI M-PHY G5 Type 1 2Tx2Rx in Samsung (14nm)

The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 …

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MIPI M-PHY Samsung 14nm Available on request View all specifications

Overview

The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI
M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The IP is optimized for a broad range of high-speed interfaces for applications including JEDEC Universal Flash Storage (UFS) and UniPro interfaces which are widely used in mobile and automotive applications.
The Synopsys M-PHY IP, ideal for embedded storage and chip-to-chip communication, provides low-power features, fast transitions between high- speed burst to low power saving modes, and the ability to manage the TX and RX directions independently.
The Synopsys MIPI M-PHY IP supports HS Gear1, Gear2, Gear3, Gear4 and Gear5 rates ranging from 1.248 Gbps to 23.32 Gbps per lane. Low-speed capabilities are available with Gear1 to Gear5 PWM modes. A sophisticated clock recovery mechanism and power-efficient clock circuitry are designed to guarantee the integrity of the clocks and signals needed to meet strict timing requirements. The Synopsys MIPI M-PHY IP supports large and small amplitudes, slew rate control and dithering functionality for optimized electromagnetic interference (EMI).
The Synopsys MIPI M-PHY IP along with Synopsys Universal Flash Storage (UFS) Host Controller IP or Synopsys MIPI UniPro Controller IP provides a single vendor UFS IP solution that designers can easily integrate into application processors with less risk, while speeding time-to-market of advanced SoCs and device integrated circuits (ICs).

Key features

  • Compliant with either the MIPI M-PHY v5.0 or MIPI M-PHY v4.1 specification as M-PHY Type-I
  • Supports MIPI UniPro, JEDEC UFS protocols
  • Supports High-Speed (HS) Gear1, Gear2, Gear3, Gear4 and Gear5 4 A/B modes
  • Low-speed Pulse-Width Modulation (PWM) Gear1 to Gear5 in Type-I LS implementation
  • Extended reference clock support: 19.2, 26, 38.4 and 52MHz
  • Optimized lower power and hibernation mode to minimize energy consumption
  • Fast entering and recovery from/to low-power modes
  • Optimized EMI performance through the use of slew rate control and dithering
  • Large and small amplitude
  • Sophisticated clock recovery mechanism
  • Power efficient clock circuitry for high-speed and low-speed clock generation
  • Supports advanced process technologies
  • Easily integrates with Synopsys MIPI UniPro and UFS Host Controller IP

Benefits

  • Compliant with MIPI M-PHY v5.0 specification
  • Supports MIPI UniPro, JEDEC UFS protocols
  • Supports High-Speed (HS) Gear1, Gear2, Gear3, Gear4 and Gear5 A/B modes
  • Supports M-PHY Type-I
  • Modular architecture allows multiple lane configurations
  • Low-speed Pulse-Width Modulation (PWM) Gear1 to Gear5 in Type-I LS implementation
  • Low-power operation, small area and low latency
  • Supports advanced process technologies
  • Easily integrates with Synopsys MIPI UniPro and UFS Host

Applications

  • Smartphones
  • Tablets, ultrabooks,
  • Automotive ADAS and infotainment
  • Chip-to-chip low-power interconnects
  • Flash Storage Devices
  • Gaming
  • Digital cameras, camcorders
  • Hard Disk Drives (HDD)
  • Wireless communication
  • Set-top boxes
  • Smart TVs
  • Drones
  • Augmented/virtual reality

What’s Included?

  • Databook
  • Application notes
  • Integration guidelines
  • Verilog behavioral model
  • Abstract LEF and timing LIB files
  • GDSII layout database

Silicon Options

Foundry Node Process Maturity
Samsung 14nm 14nm 140 nm Available on request

Specifications

Identity

Part Number
dwc_mipi_mphy_g5_type1_22_samsung
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

MIPI PHY
MIPI M-PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about MIPI PHY IP core

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.

Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP

With the rapid development of modern mobile systems there is a great increase in the complexity involved in the IP and SOC designs and correspondingly the functional verification also becomes a challenge. To reduce time to market, IPs needed for the SOC must be developed in parallel to the top level design and should be verified in parallel. This requires strong methodology and infrastructure support which allows the SOC design team to be aligned on the requirements with IP teams. Methodology should also ensure that SOC design team gets the required data for the IP to proceed with the complexity of SOC design.

Frequently asked questions about MIPI PHY IP

What is MIPI M-PHY G5 Type 1 2Tx2Rx in Samsung (14nm)?

MIPI M-PHY G5 Type 1 2Tx2Rx in Samsung (14nm) is a MIPI PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for samsung Available on request.

How should engineers evaluate this MIPI PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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