Vendor: SmartDV Technologies Category: MIPI

MIPI LLI Verification IP

MIPI LLI Verification IP is compliant with MIPI LLI specification and verifies LLI devices.

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Verification IP View all specifications

Overview

MIPI LLI Verification IP is compliant with MIPI LLI specification and verifies LLI devices. LLI Verification IP is developed by experts who have worked on complex protocols before.

MIPI LLI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI LLI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports MIPI LLI specification 1.0.
  • Support MIPI MPHY Type-I specification
  • PHY layer supports MPHY serial, MPHY RMMI (10,20,40 bit) Interface
  • PHY layer supports multi lanes, Type-I and all power modes for Mphy
  • Supports Master LLI, Slave LLI and Monitor
  • Supports all the control attributes as defined in Spec.
  • Supports data control at each layer of LLI Specification for easy debug.
  • Transaction layer supports Interconnect and Service (SVC) transactions.
  • Transaction layer supports all the Fragment types of SVC and LLI transactions as defined in Spec.
  • Data link layer Supports Transactions on LL, BE and SVC traffic classes for both Master and Slave interface
  • Data link layer supports separate flow control features for each traffic class.
  • Data link layer supports Transaction frame for exchanging LLI transactions
  • Data link layer supports Message frame for exchanging flow control information.
  • Data link layer supports priority based arbitration between LL, BE and SVC traffic classes.
  • PA layer supports all the PDUs as defined in Spec
  • PA layer supports for CRC and SEQ computation automatically.
  • PA layer supports PHITs distributions on multiple lanes as defined in Spec.
  • PA layer supports Link startup and Physical Link Update (PLU) as per Spec.
  • Master and Slave LLI supports all state transitions as defined in Spec.
  • Supports Power on Reset and Rest on Error option in both Master and Slave LLI.
  • Supports various error injections and detections scenario in all the layers of LLI Specifications.
  • Supports callbacks for user to get packets or to inject errors in Master, Slave and monitor.
  • Status counters for various events.
  • Functional coverage for each functional condition in env.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocols violations.
  • MIPI LLI verification IP comes with complete test suite to test every feature of MIPI LLI spec.

Block Diagram

MIPI LLI VIP block diagram

Benefits

  • Faster testbench development and more complete verification of MIPI LLI designs.
  • Easy to use command interface simplifies testbench control and configuration of Master,Slave and monitor
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the MIPI LLI testcases.
  • Examples showing how to connect various components, and usage of Master,Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
MIPI LLI VIP
Vendor
SmartDV Technologies
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about MIPI IP cores

What is MIPI LLI Verification IP?

MIPI LLI Verification IP is a MIPI IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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