MIPI DSI-2 Synthesizable Transactor

MIPI DSI-2 Synthesizable Transactor provides a smart way to verify the MIPI DSI-2 bi-directional two-wire bus component of a SOC or a ASIC in Emulator or FPGA platform.The SmartDV's MIPI DSI-2 Synthesizable Transactor is fully compliant with version 1.1 MIPI Alliance specification for serial Interface and provides the following features.

• Full MIPI DSI-2 Tx and Rx functionality.
• Supports MIPI DSI-2 Specification.
• Support both DPHY and CPHY
• Supports MIPI DBI specification
• Supports MIPI DCS specification
• Supports all types of D-PHY short packets
• Supports all types of D-PHY long packets
• Supports all types of C-PHY short packets
• Supports all types of C-PHY long packets
• Supports all lane configuration
• Supports multiple packets per transmission
• Supports differential and single ended mode of operation
• Supports PPI interface
• Supports all BTA commands
• Supports Link Distribution Function
• Supports skew calibration
• Supports Display Stream Compression (DSC)
• Various kind of Tx and Rx errors generation and detection
• SoT error
• Sync error
• Word count error
• Sync length error
• Checksum error
• ECC error
• Supports detection of all timeouts and injection of various timeout errors
• Supports both high speed and low power packet transmission and reception
• Supports fine grain control of timing parameters
• Operates as a Tx,Rx, or both.

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the MIPI DSI-2 testcases
• Examples showing how to connect various components,and usage of Synthesizable Transactor
• Detailed documentation of all DPI,class,task and functions used in verification env
• Documentation contains User's Guide and Release notes