Vendor: SmartDV Category: MIPI

MIPI DEBUG Synthesizable Transactor

MIPI DEBUG Synthesizable Transactor provides a smart way to verify the MIPI DEBUG component of a SOC or a ASIC in Emulator or FPG…

Overview

MIPI DEBUG Synthesizable Transactor provides a smart way to verify the MIPI DEBUG component of a SOC or a ASIC in Emulator or FPGA platform. MIPI DEBUG Synthesizable Transactor provides an smart way to verify the MIPI DEBUG bi-directional two-wire bus. The SmartDV's MIPI DEBUG Synthesizable Transactor is fully compliant with Specification for DEBUG version 1.0 and provides the following features.

Key features

  • Compliant with MIPI Debug version 1.0 specification.
  • Full MIPI Debug functionality.
  • Support full I3C Slave with CCC, Hot Join, IBI, DAA and HDR mode.
  • Full Link and Network/Transport layer.
  • Support Network adaptors for following
    • SPP
    • STP
    • SAM
    • TWP
    • UART
  • Supports upto 16 Network Adaptors
  • Supports error detection and recovery

Block Diagram

MIPI Debug Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the MIPI DEBUG testcases
  • Examples showing how to connect various components, and usage of Synthesiable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
MIPI Debug Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about MIPI IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about MIPI IP cores

What is MIPI DEBUG Synthesizable Transactor?

MIPI DEBUG Synthesizable Transactor is a MIPI IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP