Vendor: Synopsys, Inc. Category: MIPI PHY

MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)

Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and per…

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MIPI D-PHY TSMC 40nm ULP eFlash Available on request View all specifications

Overview

Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for mobile, automotive, artificial intelligence (AI), and IoT applications. The PHY, for mainstream and FinFET processes, is compliant with the D-PHY specification, operating at 10Gb/s aggregate data rate in 4 lanes. Supporting low-power state modes allows the IP to deliver low-power consumption at the maximum speed to address energy requirements of battery-operated devices. The Synopsys
D-PHY IP interoperates with Synopsys’ CSI-2 and DSI/DSI-2 controllers which support key features of the latest MIPI display and camera specifications. The Synopsys MIPI D-PHY IP is ASIL B Ready ISO 26262 certified, meeting the stringent requirements of automotive ADAS and Infotainment applications.

Key features

  • Compliant with the MIPI D-PHY specification
  • Fully verified hard macro
  • Up to 2.5 Gb/s per lane
  • Aggregate throughput up to 10 Gb/s in 4 data lanes
  • Support for the PHY Protocol Interface (PPI)
  • Low-power escape modes and ultra- low-power modes
  • Shutdown mode
  • SCAN and Loopback BIST modes
  • Extensive access to internal programmability registers

Benefits

  • Compliant with the MIPI D-PHY specification, v1.2
  • Fully integrated hard macro
  • Up to 2.5 Gbps per lane
  • Aggregate throughput up to 10 Gbps in 4 data lanes
  • Supports PHY Protocol Interface (PPI)
  • Low-power escape modes and ultra low- power state modes
  • Shutdown mode
  • SCAN and loopback BIST modes
  • Extensive access to internal programmability registers
  • Master, slave, TX- and RX-only configurations
  • Attachable PLL for master applications
  • Flexible input clock reference
  • 50% DDR output clock duty cycle
  • Silicon-proven, robust design available in advanced process technologies
  • ASIL B Ready ISO 26262 certified for Grade 1 and Grade 2 automotive design

Applications

  • CSI-2 Host
  • DSI Host
  • CSI-2 Device
  • DSI Device

What’s Included?

  • Databook
  • Behavioral model
  • LEF file
  • .LIB file
  • GDSII Layout Database

Silicon Options

Foundry Node Process Maturity
TSMC 40nm ULP eFlash Available on request

Specifications

Identity

Part Number
dwc_mipi_dphy_rx2_tsmc
Vendor
Synopsys, Inc.
Type
Silicon IP

Standards & Interfaces

MIPI PHY
MIPI D-PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA
Contact Synopsys, Inc.

Learn more about MIPI PHY IP core

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.

Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP

With the rapid development of modern mobile systems there is a great increase in the complexity involved in the IP and SOC designs and correspondingly the functional verification also becomes a challenge. To reduce time to market, IPs needed for the SOC must be developed in parallel to the top level design and should be verified in parallel. This requires strong methodology and infrastructure support which allows the SOC design team to be aligned on the requirements with IP teams. Methodology should also ensure that SOC design team gets the required data for the IP to proceed with the complexity of SOC design.

Frequently asked questions about MIPI PHY IP

What is MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)?

MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6) is a MIPI PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for tsmc Available on request.

How should engineers evaluate this MIPI PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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