Vendor: Xilinx, Inc. Category: MIPI

MIPI CSI-2 RX Controller Subsystem

The Xilinx MIPI CSI2 Receiver Subsystem implements the Mobile Industry Processor Interface (MIPI) based Camera Serial Interface (…

Overview

The Xilinx MIPI CSI2 Receiver Subsystem implements the Mobile Industry Processor Interface (MIPI) based Camera Serial Interface (CSI-2) according to version 1.1 on Xilinx's UltraScale+ devices and allows users to capture raw images from MIPI CSI2 camera sensors. The CSI2 Receiver can be implemented in Xilinx UltraScale+ FPGAs without requiring expensive external D-PHY bridges. The output of the CSI2 subsystem is AXI4 based sensor data ready for image sensor processing. The subsystem allows fast selection of the top level parameters and automates most of the lower level parameterization. The AXI4 streaming interfaces makes it easy for other AXI4 based subsystems to seamlessly plug into the CSI receive controllers.

Key features

  • Support for 1 to 4 PPI Lanes
  • Line rates ranging from 80 to 1500 Mb/s
  • Multiple data type support (RAW,RGG,YUV)
  • AXI IIC support for CCI interface
  • Filtering based on Virtual Channel ID (VC)
  • Single, Dual, Quad pixel support at output
  • Interface compliant to UG934 format with support for 4K resolution imagers
  • Small resource count

Specifications

Identity

Part Number
EF-DI-MIPI-CSI-RX-SITE
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: USA

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Frequently asked questions about MIPI IP cores

What is MIPI CSI-2 RX Controller Subsystem?

MIPI CSI-2 RX Controller Subsystem is a MIPI IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this MIPI?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.

Can this semiconductor IP be compared with similar products?

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