MIPI BIF Master IIP

MIPI BIF Master interface provides full support for the two-wire MIPI BIF synchronous serial interface, compatible with BIF 1.0 specification. Through its BIF compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI BIF Master IIP is proven in FPGA environment. The host interface of the MIPI BIF can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI BIF Master IIP is supported natively in Verilog and VHDL

• Complaint with 1.0 MIPI BIF Specification
• Full MIPI BIF Master functionality
• Supports following frames
• Reset
• Power control
• Interrupt
• Burst
• Multicast
• UID search
• Device specific command
• Supports Low power modes
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The MIPI BIF Master interface is available in Source and netlist products.
• The Source product is delivered in plain text verilog or VHDL or SystemC source code
• Easy to use Verilog Test Environment with Verilog Testcases.
• Lint, CDC, Synthesis, Simulation Scripts with waiver files.
• IP-XACT RDL generated address map.
• Firmware code and Linux driver package.
• Documentation contains User's Guide and Release notes.
• ISO26262 Safety Manual (SAM) Document
• ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA)Document