Vendor: Teletrx Category: Video Transport

MIPI A-PHY

MIPI A-PHY

Key features

  • Asymmetric data link layer with point-to-point or daisy-chain topology
  • Up to 15-meter reach
  • Support 3 downlink speed gears Gear 1.0/2.0/3.0(2, 4, 8Gbps) 
  • 2 uplink speed gears (100 and 200 Mbps)
  • Ultra-low packet error rate (PER) of 10-19 for unprecedented reliability over vehicle lifetime
  • High-speed data, control data and optional power share the same physical wiring
  • Reduces complexity, cost, wiring and weight

Benefits

  • Expands PAM4 encoding to lower gears, reducing the operating signal rate of these gears and allowing implementation of A-PHY using lower cost legacy cables and connectors.

Applications

  • Targeted for ADAS/ADS surround sensor applications and Infotainment display applications in automotive

Specifications

Identity

Part Number
MIPI A-PHY
Vendor
Teletrx
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Taiwan (R.O.C.)

Learn more about Video Transport IP core

High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems

Many video systems are implemented with feature-rich FPGA and multi-rate SDI integrated circuits that support high performance professional video transport over long distances. But FPGAs demand high density routing with fine trace width while high-speed analog SDI routing demands impedance matching and signal fidelity. This paper outlines the layout challenges facing hardware engineers and provides recommendations for dealing with these challenges.

A 24 Processors System on Chip FPGA Design with Network on Chip

In this paper we present a single FPGA chip implementation of a NOC based shared memory multiprocessor system with 24 processors connected to a main memory composed of 4 DDR2 banks. All the processors and DDR2 memories are connected to a NOC through Open Core Protocol (OCP-IP) interface. The MPSOC have been validated and evaluated through actual execution with matrix multiplication application. A Global Asynchronous Local Synchronous (GALS) design methodology have been adopted throughout the design cycle and exploited for clock trees designs.

STBus complex interconnect design and verification for a HDTV SoC

To support High Definition Television (HDTV) application, the System on Chip (SoC) presented in this paper has to support multiple and concurrent internal processes. Most of these operations read data from memory, process them and store the resulting data into memory. Each functional unit of the system is responsible for a specific data processing, but all the data are stored in the same shared external memories.

Audio Coding for Wireless Applications

This paper discusses wireless audio transmission and the issues that need consideration, and suggests the apt-X algorithm as an appropriate and advantageous coding solution.

A comparison of Network-on-Chip and Busses

This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures

Frequently asked questions about Video Transport IP cores

What is MIPI A-PHY?

MIPI A-PHY is a Video Transport IP core from Teletrx listed on Semi IP Hub.

How should engineers evaluate this Video Transport?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Transport IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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