Memory & Bus Protection IP Core
The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
Overview
The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
It supports AHB/AXI slave/master interfaces, APB port for configuration purpose, and contains a cache. It is typically placed between the processor(s) and an external memory controller (DDRx). This IP Core improves tamper resistance by avoiding any modification, spoofing or analysis of external data.
Implementation aspects
The processor can securely and transparently write/read data or code from external memory. It leverages the AES Core from Secure-IC. The unique architecture enables a high level of flexibility (cache size, performances) and allows it to be used by microcontroller and multi-core architectures. The features required by a specific application can be taken into account in order to select the most optimal configuration for any FPGA or ASIC technology.
Key features
- Protect the external memory
- On-the-fly encryption/decryption and authentication
- Transparent for the processor
- Scalable data bus width (32, 64, 128 bits)
- AMBA Master/Slave interfaces
- Supports all key sizes (128/192/256 bits)
- Scalable internal Cache
- ASIC and FPGA
Block Diagram
Applications
- Embedded security processor
- Secure payment
What’s Included?
- Netlist or RTL
- Scripts for synthesis & STA
- Self-checking RTL test-bench on referenced vectors
- Documentation
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Security Coprocessor IP core
Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
Security in vehicular systems
A Comprehensive Post-Quantum Cryptography (PQC) Solution based on Physical Unclonable Function (PUF)
The Fundamentals of a SHA-256 Master/Slave Authentication System
Frequently asked questions about Security Coprocessor IP cores
What is Memory & Bus Protection IP Core?
Memory & Bus Protection IP Core is a Security Coprocessor IP core from Secure-IC listed on Semi IP Hub.
How should engineers evaluate this Security Coprocessor?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Security Coprocessor IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.