How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
LPSDR Memory Model
LPSDR Memory Model provides an smart way to verify the LPSDR component of a SOC or a ASIC.
Overview
LPSDR Memory Model provides an smart way to verify the LPSDR component of a SOC or a ASIC. The SmartDV's LPSDR memory model is fully compliant with standard LPSDR Specification and provides the following features. Better than Denali Memory Models.
LPSDR Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
LPSDR Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports LPSDR memory devices from all leading vendors.
- Supports 100% of LPSDR protocol standard LPSDR specification.
- Supports all the LPSDR commands as per the LPSDR specification.
- Supports following device density
- 512MB
- 1GB
- Supports following device modes.
- X16 Mode
- X32 Mode
- Supports programmable burst lengths: 1, 2, 4, 8, and continuous
- Supports following burst type,
- Sequential
- Interleaved
- Supports deep power down mode.
- Supports Auto-Refresh and Self-Refresh mode.
- Supports programmable partial array self refresh
- Supports burst termination operation.
- Supports clock suspend operation.
- Supports all data rates as per specification.
- Supports programmable clock frequency of operation.
- Checks for following
- Check-points include power up, initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Supports callbacks for user to get command data on bus.
- Supports all mode registers programming
- Supports power down features.
- Supports input clock stop and frequency change.
- Quickly validates the implementation of the LPSDR standard LPSDR specification.
- Bus-accurate timing for min, max and typical values.
- Constantly monitors LPSDR behavior during simulation.
- Protocol checker fully compliant with LPSDR specification.
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor
Block Diagram
LPSDR Memory Model block diagram
Benefits
- Faster testbench development and more complete verification of LPSDR designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the LPSDR testcases.
- Complete UVM/OVM sequence library for LPSDR controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
LPSDR Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is LPSDR Memory Model?
LPSDR Memory Model is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.