Vendor: SmartDV Technologies Category: Protocol Bridge

LPDDR5 DFI Assertion IP

LPDDR5 DFI Assertion IP provides an efficient and smart way to verify the DFI LPDDR5 designs quickly without a testbench.

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Overview

LPDDR5 DFI Assertion IP provides an efficient and smart way to verify the DFI LPDDR5 designs quickly without a testbench. The SmartDV's LPDDR5 DFI Assertion IP is fully compliant with DFI version 5.0 Specifications.

LPDDR5 DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR5 DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Compliant with DFI version 5.0 Specifications.
    • Supports LPDDR5 devices compliant with JEDEC LPDDR5 SDRAM Standard JESD209-5.pdf, JESD209-5A and LPDDR5X (Draft).
    • Supports for Read data bus inversion.
    • Supports for Write data bus inversion.
    • Supports for DFI disconnect during training.
    • Supports for WCK Control interface.
    • Supports write clock free running mode.
    • Supports data copy low power function and write x operation.
    • Supports for 2:1 and 4:1 CKR mode.
    • Supports all data rates as per specification.
    • Supports write data mask operation.
    • Supports WCK2CK Sync operation.
    • Supports deep sleep mode.
    • Supports power down mode and self-refresh operation.
    • Supports programmable clock frequency of operation.
    • Supports following training modes.
    • Command bus training
    • WCK2CK leveling
    • WCK-DQ training
    • Enhanced RDQS training mode
    • Supports Error signaling.
    • Supports all types of timing and protocol violations detection for timing parameters.
    • Constantly monitors DFI behavior during simulation.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Control mode, PHY mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV DFI LPDDR5 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure DFI LPDDR5 Assertion IP functionality.

Block Diagram

LPDDR5 DFI AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
LPDDR5 DFI AIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about Protocol Bridge IP cores

What is LPDDR5 DFI Assertion IP?

LPDDR5 DFI Assertion IP is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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