Vendor: SmartDV Technologies Category: Protocol Bridge

LPDDR4 DFI Assertion IP

LPDDR4 DFI Assertion IP provides an efficient and smart way to verify the DFI LPDDR4 designs quickly without a testbench.

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Overview

LPDDR4 DFI Assertion IP provides an efficient and smart way to verify the DFI LPDDR4 designs quickly without a testbench. The SmartDV's LPDDR4 DFI Assertion IP is fully compliant with DFI version 4.0 or 5.0 Specifications.

LPDDR4 DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR4 DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Compliant with DFI version 4.0 or 5.0 Specifications.
    • Supports LPDDR4 devices compliant with JEDEC LPDDR4 SDRAM Standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4X and LPDDR4Y (Proposed).
    • Supports for Read data-eye training
    • Supports for Read gate training
    • Supports for Write leveling
    • Supports for Write date-eye training
    • Supports for CA training
    • Supports for Read data bus inversion
    • Supports for Write data bus inversion
    • Supports for Combined and multi-configuration channel support
    • Supports for DFI disconnect during training
    • Supports for Write data mask and data strobe features..
    • Supports for ZQ/DQ Calibration commands.
    • Supports for Byte mode.
    • Supports for Single-ended mode.
    • Supports for Power Down features.
    • Supports for Self refresh.
    • Supports for Programmable READ/WRITE Latency timings.
    • Supports for both 16 and 32 Programmable burst lengths.
    • Supports for Burst sequence.
    • Supports Error signaling.
    • Supports Independent Operation & Multi-Configuration Support for LPDDR4.
    • Supports all types of timing and protocol violations detection for timing parameters.
    • Constantly monitors DFI behavior during simulation.
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Control mode, PHY mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV DFI LPDDR4 VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure DFI LPDDR4 Assertion IP functionality.

Block Diagram

LPDDR4 DFI AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
LPDDR4 DFI AIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

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Frequently asked questions about Protocol Bridge IP cores

What is LPDDR4 DFI Assertion IP?

LPDDR4 DFI Assertion IP is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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