Vendor: SmartDV Category: Protocol Bridge

LPDDR3 DFI Synthesizable Transactor

LPDDR3 DFI Synthesizable Transactor provides a smart way to verify the LPDDR3 DFI component of a SOC or a ASIC in Emulator or FPG…

Overview

LPDDR3 DFI Synthesizable Transactor provides a smart way to verify the LPDDR3 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR3 DFI Synthesizable Transactor is fully compliant with standard DFI version 3.1 or higher Specifications and provides the following features.

Key features

  • Compliant with DFI version 3.1 or higher Specifications.
  • Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
  • Supports for Read data-eye training.
  • Supports for Read gate training.
  • Supports for Write date-eye training.
  • Supports for CA training.
  • Supports for DFI disconnect during training.
  • Supports for write data mask and data strobe features.
  • Supports for Power Down features.
  • Supports for Deep Power Down features.
  • Supports all data rates as per specification.
  • Supports for Burst sequence.
  • Supports for Write leveling.
  • Supports for X16 and X32 mode.
  • Supports DRAM Clock disabling feature.
  • Supports Error signaling.
  • Supports all types of timing and protocol violations detection for timing parameters.
  • Protocol checker fully compliant with DFI 3.1 or higher Specifications.

Block Diagram

LPDDR3 DFI Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the LPDDR3 DFI testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
LPDDR3 DFI Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Protocol Bridge IP core

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As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about Protocol Bridge IP cores

What is LPDDR3 DFI Synthesizable Transactor?

LPDDR3 DFI Synthesizable Transactor is a Protocol Bridge IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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