JTAG Slave To AHB Bridge IIP
JTAG Slave To AHB Bridge interface provides full support for the two-wire JTAG synchronous serial interface, compatible with Jtag…
Overview
JTAG Slave To AHB Bridge interface provides full support for the two-wire JTAG synchronous serial interface, compatible with Jtag protocol standard IEEE 1149.1 and IEEE 1149.6. Through its JTAG compatibility, it provides a simple interface to a wide range of low-cost devices. JTAG Slave To AHB Bridge IIP is proven in FPGA environment.The host interface of the JTAG can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
JTAG Slave To AHB Bridge IIP is supported natively in Verilog and VHDL
Key features
- Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6
- Supports all the JTAG tap instructions.
- Supports programmable clock frequency of operation.
- Supports Instruction register and data register of various sizes.
- Converts JTAG into AHB write and read to access AHB bus
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
Block Diagram
Benefits
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
What’s Included?
- The JTAG Slave To AHB Bridge interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Protocol Bridge IP cores
What is JTAG Slave To AHB Bridge IIP?
JTAG Slave To AHB Bridge IIP is a Protocol Bridge IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.