Vendor: SmartDV Category: Test / Debug

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor provides a smart way to verify the JTAG component of a SOC or a ASIC in Emulat…

Overview

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor provides a smart way to verify the JTAG component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor is fully compliant with standard JTAG Specification and provides the following features.

Key features

  • Follows JTAG basic specification as defined in JTAG Specification 3
  • Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6
  • Supports all the JTAG tap instructions
  • Supports programmable clock frequency of operation
  • Supports checks for following
    • Check-points include Initialization rules
    • State based rules,Active Command rules
    • Read/Write to Instruction and data register Rules
  • Supports instruction register and data register of size up to 64 bits
  • Supports proficiency to extend with user defined instructions and registers
  • Has ability to read BSDL file and
    • Automatically generate testvectors to test all BSDL cell types
    • Automatically generate SVA assertions properties
  • Supports all types of timing and protocol violation detection

Block Diagram

JTAG (IEEE 1149.1/1149.6) Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the JTAG (IEEE 1149.1/1149.6) testcases
  • Examples showing how to connect and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation also contains User's Guide and Release notes

Specifications

Identity

Part Number
JTAG (IEEE 1149.1/1149.6) Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Test / Debug IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about SerDes Test / Debug IP cores

What is JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor?

JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor is a Test / Debug IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Test / Debug?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Test / Debug IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP