Vendor: Techno Mathematical Co., Ltd. Category: Video Processing

JPEG XS Decoder (FPGA) - Performance-oriented version

TMC’s JPEG XS IP maximizes the advantages of FPGAs and helps customers improve the competitiveness of their products.

Overview

The demand for high-resolution imaging beyond 4K continues to grow across medical diagnostic equipment,
broadcasting systems, and surveillance cameras.
This trend creates challenges in maintaining high image quality while improving data transfer speeds and reducing storage costs.

TMC’s JPEG XS IP cores address these challenges through:

  • FPGA-optimized dedicated designs
  • Ultra-low latency real-time processing
  • Versatile implementation options for diverse applications
  • Two specialized versions: Standard and Performance-oriented

TMC’s JPEG XS IP maximizes the advantages of FPGAs and helps customers improve the competitiveness of their products.

Specification

Compression Format JPEG XS (ISO/IEC21122-1)
Profile Light422.10, Light444.12, Main422.10, Main444.12, High444.12
Throughput 8sample/clock(Standard version)
12sample/clock(Performance-oriented version)
Maximum Image Size 4096 × 2160 pixel
Frame Rate 60fps
Image Format RGB、YCbCr4:4:4/4:2:2/4:0:0
Bit Depth 8/10/12bit
Compressed Ratio 1/2 to 1/20 (adjustable per frame)
Compression Method CBR (Fixed by frame)
Interface Specification AXI4-Stream

This IP supports both color spaces of YCbCr and YUV.

Contents of Two Types

  • Standard
    Operating frequency : 150MHz(YCbCr4:2:2,YCbCr4:0:0), 240MHz(RGB,YCbCr4:4:4)
  • Performance-oriented
    Operating frequency : 150MHz (all formats/bit depth)
    while other companies’ IPs require 240MHz for RGB and YCbCr4:4:4

Key features

  • Advanced Processing: Handles 4K/60p on Kintex UltraScale+ or Arria10 class FPGAs
    Also available for devices from Lattice, Efinix, and Microchip.
  • Flexible IP Options: Offers standard and high-performance IP, with lightweight versions optimized for broadcast (YCbCr 4:2:2) and industrial (YCbCr 4:0:0) applications
  • Proven Technology: Leverages our expertise from years of codec development
  • Memory Efficiency: Requires no external memory, eliminating complex timing and bandwidth design
  • Simple Integration: Streamlined interface for easy embedding and faster development

Specifications

Identity

Part Number
TM22366
Vendor
Techno Mathematical Co., Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is JPEG XS Decoder (FPGA) - Performance-oriented version?

JPEG XS Decoder (FPGA) - Performance-oriented version is a Video Processing IP core from Techno Mathematical Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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