Vendor: Techno Mathematical Co., Ltd. Category: Video Processing

JPEG XS Decoder (FPGA) - Performance-oriented version

The demand for high-resolution imaging beyond 4K continues to grow across medical diagnostic equipment, broadcasting systems, and…

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Overview

The demand for high-resolution imaging beyond 4K continues to grow across medical diagnostic equipment, broadcasting systems, and surveillance cameras.
This trend creates challenges in maintaining high image quality while improving data transfer speeds and reducing storage costs.

The JPEG XS IP cores address these challenges through:

  •  FPGA-optimized dedicated designs
  •  Ultra-low latency real-time processing
  •  Versatile implementation options for diverse applications
  •  Two specialized versions: Standard and Performance-oriented

The JPEG XS IP maximizes the advantages of FPGAs and helps customers improve the competitiveness of their products.

Key features

  • Memory Efficiency:No external memory required, eliminating complex timing and bandwidth design
  • Simple Integration: Streamlined interface for fast development
  • Advanced Processing: 4K/60p capability on Kintex UltraScale+ or Arria10 FPGAs
  • Proven Technology: Built on our established expertise in codec development

Specifications

Identity

Part Number
TM22366
Vendor
Techno Mathematical Co., Ltd.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Techno Mathematical Co., Ltd.

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is JPEG XS Decoder (FPGA) - Performance-oriented version?

JPEG XS Decoder (FPGA) - Performance-oriented version is a Video Processing IP core from Techno Mathematical Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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