GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes.
- MIPI D-PHY
- GlobalFoundries
- 22nm
- FDX
- Pre-Silicon
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock a…
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Master V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices.
10G Unmanaged Ethernet Switch IP core (10G UES) is an evolution of our 1G Unmanaged Ethernet Switch IP Core (UES).
Dolphin Technology provides JTAG Controller (TAP) IP which enables access through the JTAG interface for building designs with ef…
Universal Synchnonous/Asynchronous Receiver Transmitter (UART/USART)
Dolphin Technology provides Universal Synchnonous/Asynchronous Receiver Transmitter (UART/USART) IP which allows the communicatio…
General Purpose Input/Output (GPIO) Controller
Dolphin Technology provides General Purpose I/O IP which cosists of up to 32 I/O ports that can be programmed individually for in…
The Actt's 16G SerDes IP is a high performance Multi-lane SerDes PHY IP designed for chips that perform high bandwidth data commu…
The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels.
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure co…
GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer …
GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface …
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure co…
ARINC664 Switch IP implements ARINC664 part 7 and provides switching functionality within the ARINC664 network.
ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 ne…
Digital audio PDM-to-PCM converter with 117 dB Dynamic Range and Dual-phase alignment
The YANZI-D-octDSA-YA3-VD.01 is a PDM-to-PCM converter to interface with digital microphones.